Microprocessor technology continues to advance at a rapid pace, with consideration given to all aspects of design. Designers constantly strive to increase performance, while maximizing efficiency. With respect to performance, greater overall microprocessor speed is achieved by improving the speed of various related and unrelated microprocessor circuits and operations, including parallel and out-of-order operations. With respect to efficiency, the size of the microprocessor integrated circuit is constantly scrutinized to produce a smaller and, therefore, more efficient device. The present embodiments provide enhancements in both of these areas, as well as others which will be appreciated by a person skilled in the art.
The present embodiments relate in general to microprocessors, and are more specifically directed to information storage in such devices. Microprocessor technology to date has included various approaches to information storage. For example, a common current microprocessor includes various hierarchical levels of storage, beginning at the lowest level using registers, ascending through one or more levels of queues and/or caches, and up to some high level storage such as large memory structures which are both on and off the same integrated circuit which forms the microprocessor. Many of these varying levels represent various benefits, but each often also includes some drawbacks, such as added complexity, added area on the integrated circuit, inflexibility in size, and so forth.
In view of the above, the present inventors address the drawbacks of certain prior microprocessor information storage circuits, as demonstrated below.